1. Field of the Invention
Example embodiments relate to a liquid crystal display (LCD) device, and more particularly, to a source driver included in a LCD device, an output buffer included in the source driver, and a method of operating the output buffer.
2. Description of the Related Art
Liquid crystal display (LCD) devices generally are smaller, thinner, and require less power than the other types of conventional display devices. Accordingly, LCD devices are applied to electronic apparatuses such as notebook computers and mobile phones, for example. In particular, active matrix type LCD devices that use thin film transistors (TFTs) as switch devices are suitable for moving image displays.
FIG. 1 is a block diagram of a conventional LCD device 100. Referring to FIG. 1, the LCD device 100 includes an LCD panel 110, a gate driver circuit 120, and a source driver circuit 200.
The gate driver circuit 120 generates a plurality of signals G1, G2, . . . , Gp for driving a plurality of gate lines GL arranged on the LCD panel 110. The source driver circuit 200 generates source line driving signals S1, S2, . . . , Sm for driving a plurality of source lines SL arranged on the LCD panel 110. The source lines are also referred to as data lines or channels.
The LCD panel 110 includes a plurality of pixels 111. Each of the pixels 111 includes a switch transistor TFT and a liquid crystal capacitor CLC. The switch transistor TFT is turned on or off in response to a signal that drives the gate line GL, and a source terminal of the switch transistor TFT is connected to the source line SL. The liquid crystal capacitor CLC is connected between a drain terminal of the switch transistor TFT and a source of common voltage VCOM. For example, the common voltage VCOM may transition from logic high to logic low (or from logic low to logic high) for every horizontal scan period.
FIG. 2 is a circuit diagram of the source driver circuit 200 illustrated in FIG. 1. Referring to FIG. 2, the conventional source driver circuit 200 includes a polarity inversion circuit 210, a latch circuit 220, a gray-scale voltage generator 230, a gamma decoder circuit 240, an output buffer circuit 250, a plurality of first switches 260, a plurality of second switches 270, an intermediate voltage generator 280, and a capacitor 290.
The polarity inversion circuit 210 includes a plurality of exclusive OR (XOR) gates. The polarity inversion circuit 210 receives a plurality of pieces of n-bit image data D1[n:1], D2[n:1], . . . , Dm[n:1]. The polarity inversion circuit 210 may or may not invert image data D1[n:1], D2[n:1], . . . , Dm[n:1], in response to a polarity control signal M.
The latch circuit 220 includes a plurality of D latches. The latch circuit 220 latches data received from the polarity inversion circuit 210 and outputs the latched data in response to a latch control signal S_LATCH.
The gray-scale voltage generator 230 generates 2n analog gray-level voltages VG and applies them to the gamma decoder circuit 240.
The gamma decoder circuit 240 includes a plurality of gamma decoders. Each of the gamma decoders selects one of the 2n analog gray-level voltages VG, which corresponds to an output digital value of the corresponding D latch included in the latch circuit 220, and then outputs the selected analog gray-level voltage VG.
The output buffer circuit 250 includes a plurality of output buffers 301, 302, . . . , 30m. Each of the output buffers 301, 302, . . . , 30m uses a boosted voltage AVDD and ground voltage VSS for supply of power. The boosted voltage AVDD is generated using supply voltage VDD applied from the outside of the source driver circuit 200. The output buffers amplify analog image signals received from the gamma decoders and supply the amplified analog image signals A1, A2, . . . , Am to the first switches 260, respectively.
The first switches 260 respectively supply the amplified analog image signals A1, A2, . . . , Am as the source line driving signals S1, S2, . . . , Sm in response to an activated control signal GRAY_ON. The source line driving signals S1, S2, . . . , Sm are supplied to equivalent load capacitance Ceq connected to the source lines of the LCD device 100 illustrated in FIG. 1.
The intermediate voltage generator 280 receives an intermediate gray-level voltage VGC from among the 2n analog gray-level voltages VG generated by the gray-scale voltage generator 230, and generates intermediate voltage VCI using the supply voltage VDD applied from the outside of the source driver circuit 200. The intermediate voltage VCI is applied to the second switches 270.
Each of the second switches 270 outputs the intermediate voltage VCI received from the intermediate voltage generator 280 as one of the source line driving signals S1, S2, . . . , Sm in response to an activated charge recycling signal CR_ON. The source line driving signals S1, S2, . . . , Sm precharge the source lines SL of the LCD device 100 to the intermediate voltage VCI.
The charge recycling signal CR_ON may be an inverted signal of the output control signal GRAY_ON. Since the charge recycling signal CR_ON is activated before the output control signal GRAY_ON is activated, the intermediate voltage VCI is applied to the source line SL before each of the amplified analog image signals A1, A2, . . . , Am is supplied to the corresponding equivalent load capacitance Ceq connected to the source line SL.
The capacitor 290 stabilizes the intermediate voltage VCI, thus reducing and/or preventing oscillation of the intermediate voltage VCI. Also, whenever the second switch 270 is activated (or is closed), the capacitor 290 may be supplied with electric charges stored in a source line SL having a voltage greater than the intermediate voltage VCI and supply the electric charges to a source line SL having a voltage less than the intermediate voltage.
The conventional source driver circuit 200 includes source drivers that generate the source line driving signals S1, S2, . . . , Sm. Each of the source drivers includes the XOR gate, the D latch, the gamma decoder, the output buffer, the first switch 260, and the second switch 270.
The digital image data D1[n:1], D2[n:1], . . . , Dm[n:1], the polarity control signal M, the latch control signal S_LATCH, the output control signals GRAY_ON, and the charge recycling signals CR_ON may be generated by a timing controller (not shown) included in the LCD 100. The timing controller controls the operation timing of the source driver circuit 200.
The second switches 270, the intermediate voltage generator 280, and the capacitor 290 control the source driver circuit 200 to perform a charge recycling operation. In the charge recycling operation, the voltage of a source line driving signal does not transition from a high voltage directly to a low voltage or from the low voltage directly to the high voltage. Instead, the voltage of the source line driving signal transitions from the high voltage to the intermediate voltage VCI and then to the low voltage. The intermediate voltage VCI is a voltage having a value between the high voltage and low voltage. Alternatively, the voltage of the source line driving signal transitions from the low voltage to the intermediate voltage and then to the high voltage. The charge recycling operation reduces the consumption of power in the output buffer circuit 250.
FIG. 3 is a timing diagram illustrating an operation of the conventional source driver illustrated in FIG. 2. The operation of the source driver will now be described with reference to FIGS. 2 and 3.
Referring to FIG. 3, a polarity control signal M is toggled in time duration units of horizontal scan periods HP.
A latch control signal S_LATCH that transitions to a high value during the horizontal scan period HP causes an amplified analog image signal Am to be generated by the output buffer 30m. The polarity of the amplified analog image signal Am may or may not be inverted based on the logic state of the inverted control signal M. The amplified analog image signal Am may be data that swings the full degree between a high voltage VH and a low voltage VL, such as black image data.
In a charge recycling period RP in which a charge recycling signal CR_ON is activated to logic high and thus the second switch 270 is short-circuited, an intermediate voltage VCI is applied to a source line connected to the second switch 270. Then, a source line driving signal Sm transitions from the high voltage to the intermediate voltage VCI or from the low voltage VL to the intermediate voltage VCI.
In a driving period DP in which an output control signal GRAY_ON is activated to logic high and thus the first switch 260 is short-circuited, the amplified analog image signal Am is applied to the source line connected to the first switch 260. Then, the source line driving signal Sm transitions from the intermediate voltage VCI to the low voltage VL (image data having a logic “low” level) or from the intermediate voltage VCI to the high voltage VH (image data having a logic “high” level).
FIG. 4 is a circuit diagram illustrating in greater detail the output buffer 30m illustrated in FIG. 2. Referring to FIG. 4, the output buffer 30m includes a first input stage 310, a second input stage 320, and an output stage 330.
The output buffer 30m is a differential amplifier having a voltage follower configuration in which an amplified analog image signal Am output from the output buffer 30m is fed back to the first input stage 310 as an inverted input signal which is one of input signals input to the first input stage 310.
A plurality of first bias current sources 311 drive the first input stage 310. A second bias current source 321 drives the second input stage 320, and a bias voltage 322 of the second input stage 320 controls quiescent current IB3 flowing through the output stage 330 to be generated. The quiescent current (direct current) IB3 is current in a steady state. The steady state refers to a state in which the voltage of an input signal IN supplied to the output buffer 30m is equal to the voltage of the amplified analog image signal Am fed back to the first input stage 310. The input signal IN supplied to the output buffer 30m is received from the gamma decoder of the gamma decoder circuit 240 illustrated in FIG. 2.
The slew rate SR of the amplified analog image signal Am output from the output buffer 30m satisfies the following:SR∝(IB1/CC)  (1),wherein IB1 denotes the amount of current of the first bias current source 311 included in the first input stage 310, and CC denotes the capacitance of a compensation capacitor 331 included in the output stage 330.
The phase margin of the amplified analog image signal Am may be determined by the poles P1 and P2 of the transfer functions expressed in following Equations (2) and (3):P1∝CC  (2)P2∝(IB3/Ceq)  (3)Here, the greater the values of the poles P1 and P2, the greater the phase margin of the amplified analog image signal Am and the higher the stability of the amplified analog image signal Am.
Referring to FIG. 3, the amplified analog image signal Am must transition to the low voltage VL (or the high voltage VH) before the end of the charge recycling period RP, so that the source line driving signal Sm can rapidly transition to the low voltage VL (or the high voltage VH), whichever is a target voltage in the driving period DP. Thus, in the charge recycling period RP, the slew rate of the amplified analog image signal Am must be increased. If the capacitance CC of the compensation capacitor 331 expressed in Equation (1) decreases, the stability of the output buffer 30m also decreases as expressed in Equation (2), and therefore, the amount of the current IB1 in Equation (1) must be increased in order to increase the slew rate of the amplified analog image signal Am. Also, the slew rate of the amplified analog image signal Am may increase in proportion to the amount of current of the second bias current source 321 of the second input stage 320, and therefore, the amount of current IB2 of the second bias current source 321 must also be increased.
In the driving period DP, the equivalent load capacitance Ceq that has a comparatively large load is connected to an output of the output buffer 30m. Thus, if it is assumed that the capacitance CC of the compensation capacitor 331 is fixed in order to maintain the sufficient phase margin of the amplified analog image signal Am, the amount of the quiescent current IB3 expressed in Equation (3) must be increased.
As described above, the amount of the driving currents IB1, IB2, and IB3 flowing through the output buffer 30m increases so that the output buffer 30m can normally operate in the charge recycling period RP and the driving period DP. Therefore, a conventional output buffer 30m may lead to comparatively large power consumption.